Designing and Synthesizing a Wallace Tree Multiplier for High Speed Performance

Research areas:

• Volume 2,Issue 3, Nov. 2013

Year:

2013

Type of Publication:

Article

Keywords:

Multiplier, Multiplicand, Product, Wallace Tree, Dada, Array, Adder, Delay, Carry Look Ahead Adder

Authors:

Taye Girma

Journal:

IJAIM

Volume:

2

Number:

3

Pages:

74-77

Month:

November

ISSN:

2320-5221

Abstract:

This paper deals with design and synthesis of 8x8 Wallace Tree Multiplier. Multipliers form the heart of DSP operation and determine the performance of general-purpose microprocessors and other devices where multipliers are highly involved. However, addition is a fundamental operation of multiplier and the question is how the addition operation is performed in order to improve the speed of the multiplier. The paper proposed a new algorithm for Wallace tree multiplier as it is an efficient hardware implementation of a circuit that multiplies two integers. It consists of three stages: In the first stage, the partial product matrix is generated, and in the second stage, the partial product matrix is reduced to a height of two through taking any three wires with the same weights and input them into a full adder in the final stage, these two rows are combined using a carry look ahead adder. But, if there are two wires of the same weight left, input them into a half adder or if there is just one wire left, connect it to the next layer. The work resulted in reduction of a number of adders, which in turn resulted in reduction of delay (logic gate delay & route delay).

Full text: IJAIM_193_Final.pdf